cmos

Lecture Notes and Assignments

I have posted the lecture notes for each week in both 2-page and 3-page-with-notespace PDF formats. You can print whichever suits you. The 3-page per sheet is the PowerPoint format that gives you space to write notes beside each slide.

http://www.ele.uri.edu/Research/cherry/mentor_tutorial/

http://www.engr.uky.edu/~ee564/tutorials.htm

http://www.cse.sc.edu/~jimdavis/Courses/2005-Fall%20CSCE%20613/csce-613-fall05.htm

Lecture Week	Topics	Notes and Materials	Assignment
Week #01 (8/18)	Introduction to the subject material and the course.	Week-01 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.
Week #02 (8/23, 8/25)	Chapters 2 & 3 (start). Basic CMOS device topology and fabrication (Rabaey et al., 2002). Construction of digital logic gates in CMOS (Weste et al., 1994).	Week-02 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.	HW #1: Due 9/6. HW-01 Handout (PDF) Total 10 points.
Week #03 (8/30, 9/1)	Chapter 3, Rabaey et al. Discussion of device models for nMOS and pMOS transistors. See notes for the reading assignment.	Week-03 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.	HW #2: Due 9/13. HW-02 Handout (PDF) Total 10 points.
Week #04 (9/6, 9/8)	Chapter 3, continued. Discussion of device resistance and capacitance estimation models.	Week-04 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.	HW #3: Due 9/20. HW-03 Handout (PDF) Total 20 points.
Week #05 (9/13, 9/15)	Weste et al., Chapter 5. Discussion of transistor layout rules and examples of Boolean logic device layout using full-custom and semi-custom layout topologies.	Week-05 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.	HW #4: Due 9/27. HW-04 Handout (PDF) Total 20 points.
Week #06 (9/20, 9/22)	Rabaey, et al., Chapter 4. Discussion of wire models for the interconnect between devices and logic circuits.	Week-06 Lecture Notes (PDF): 2-page per sheet, 3-page per sheet.
Week #07 (9/27, 9/29)	Device modeling, parameterization from I-V curves, capacitance and working through homework problems.	Working design analysis problems in class. Discussing your questions on homework problems.
Week #08 (10/4, 10/6)	Tuesday: more problem-solving. Thursday: Design rules, some additional problems with capacitance and resistance.	We'll reference the problems in the Chapter from the Hodges et al. text. (Handed out two weeks ago).	Examples: Hodges, pp. 73, 78, 80. HW #5 Handout (PDF). Due 10/18.
Week #09 (10/11, 10/13)	Fall Break for part of this week.	We will will work on Assignment #4 in the lab Tuesday.	Have a good holiday and get caught up.
Week #10 (10/18, 10/20)	Power dissipation. Wire modeling - Capacitance.	We'll discuss use of design rules, and how the layout and analysis activities go together. Week 10 Lecture Notes (PDF).	HW #6 Handout (PDF). Due 10/27.
Week #11 (10/25, 10/27)	Wire modeling - Resistance. Inverters (again) - Capacitance. Exam: Review.	I'm at a conference on Tuesday, so take the time to work on assignments. Week 11 Lecture Notes (PDF). We'll discuss the exam on Thursday.	HW #7 Handout (PDF). Due 11/3. Additional Notes on HWs 6 & 7 (PDF).
Week #12 (11/1, 11/3)	Tuesday - Exam: 4 problems. Thursday: Inverters, Delay. Additional tutorials on Mentor Graphics.	Week 12 Lecture Notes (PDF).	HW #8 Mentor Tutorial: Assignment is to work through the Mentor tutorial (PDF), and turn in the output of this work process--screen dumps or printouts of created design artifacts and any other relevant output created as a result of the tutorials. For more practice with the tools, see the Mentor tutorial links at the bottom of this web page.
Week #13 (11/8, 11/10)	Projects	The project assignments come from a selection provided by the text authors, plus some that I have pulled from Rabaey et al., Chapter 11 on Computer Arithmetic combinational logic circuits. The best way to get into understanding the direct application of the material is to start on the projects. Information on the device library is given in the tutorials. Updated Mentor Design Architect tutorial document (PDF).	Here's a document discussing the project deliverables. Project Deliverables (PDF) document. Get the set of Project Guidelines (PDF) here, as they have the information about the project teams, assignment, reference materials, timeline, due dates, etc. that you will need to know. Here is the template for your project report, due at the end of the semester: Project Report Template (Word). Projects will be done in teams of two. Select a team partner.
Week #14 (11/15, 11/17)	Projects. Thursday: meet in lab 1D39.	Supplemental reading handout materials from Hodges et al. Updated Mentor Design Architect tutorial document (PDF). This is based on U. of KY web tutorial, modified for our setup.	Project Deliverables #1, 2 & 3. See the Project Deliverables & Project Guidelines documents for more information.
Week #15 (week 11/22)	Lab work on Mentor tutorial (Part 2) projects. Supplementary discussion of Hodges et al. chapters (I have Chapter 6 for you).	IC Design tutorial (PDF). This is based on U. of KY web tutorial, modified for our setup.	Project Deliverables #4 & 5. See the Project Deliverables document for more information.
Week #16 (11/29, 12/2)	Tuesday: Project work in the lab 1D39 Thursday: Discussion of Take-home exam component of the project. Discussion of the modeling and analysis of the ADDER circuits.		Project Deliverables #6 & 7. See the Project Deliverables document for more information.
Final Exam: Friday 12/9, 2:00 PM	We'll present the projects and turn in the Take Home portion of the project analysis.	Here's the Manuals for the Mentor Tools (Mentor Tools Page).	Project Final Report Due. See the Project Deliverables document for more information. Here is the template for your project report: Project Report Template (Word).